Integrated circuit semiconductor memories must of necessity operate with a high degree of reliability in order to be used in computer related applications. The production of errors on even infrequent occasions can cause serious problems in computer controlled operations and data processing. The nature of MOSFET (metal oxide semiconductor field effect transistor) memories is such that error conditions are not always consistent but frequently occur only under unique circumstances. In mass produced memory circuits certain ones of the memories will have greater resistance to error conditions while others will be more prone to the generation of errors.
Perhaps the most difficult aspect to test in semiconductor memories is that of pattern sensitivity. It is frequently the case that a particular erroneous data output produced by a semiconductor memory is caused by the pattern of data elements stored in the vicinity of the cell which produced the erroneous data output. This is primarily due to the extremely small sizes of the memory elements and numerous interconnecting lines which tend to produce parasitic capacitances. Due to the vast number of data combinations possible with even a moderate sized memory it is readily apparent that comprehensive pattern sensitivity testing can be very time consuming.
An additional error producing factor is the state of the memory cells in the previous cycle and the degree of voltage equilibration which takes place on split digit lines preceding a memory cycle. If the time for equilibration is reduced to increase the speed of the memory cycle, the degree of equalization of voltages on the digit lines is reduced and therefore, to some extent, the charge on the digit lines is dependent upon the state of the digit lines in the previous memory cycle. Since this condition is independent of pattern sensitivity it can tend to either reinforce or oppose the error voltage conditions produced by pattern sensitivity. This adds still a further dimension to the conditions under which the semiconductor memory circuit must be tested.
In most cases a semiconductor memory must be tested both by the manufacturer after fabrication and by the customer before inclusion in a product. The testing standards of the manufacturer and the customer are not necessarily the same.
As can be seen the testing of integrated circuit semiconductor memories is a necessary but heretofore time consuming operation. Therefore, there exists a need for a method and apparatus for testing a semiconductor memory circuit rapidly and efficiently to detect those circuits which cannot operate under marginal conditions. Such testing must apply the same standard of acceptability by each party performing a test of the memory circuit.
Margin testing has heretofore been accomplished with an adjustable input to measure the operating margins of stored cell voltage for each memory circuit. This testing permits anyone to sort the circuits according to margin levels. With the possibility of such sorting it is possible for customers to select the high margin circuits and reject others even though the other circuits meet manufactures specifications. The rejected low margin circuits may be returned to the manufacturer even though they are functional. This practice causes an economic loss to the manufacturer and eventually increases the costs of circuits.